Asynchronous Active Low Reset

An asynchronous reset clears a register immediately, even before the clock is running. Many ASIC libraries build their flip-flops with an active-low version of it.

This module implements a fundamental D-type flip-flop with an asynchronous active-low reset. When the reset is not asserted, the flip-flop captures the value of the data input on the rising edge of the clock and reflects it on the output. When the reset is asserted, the output immediately transitions to zero regardless of the clock signal state.

• Clock edge: posedge clk
• Reset type: Asynchronous
• Reset polarity: Active-low (rst_n)
• Output on reset: q becomes 1'b0 immediately
• Priority rules: The asynchronous reset has absolute priority over the clock and data inputs

Worked Trace:
Cycle 1: rst_n=0, clk=0, d=1 → q=0 (asynchronous reset overrides data)
Cycle 2: rst_n=1, clk=↑, d=1 → q=1 (normal capture on clock edge)
Cycle 3: rst_n=1, clk=↑, d=0 → q=0 (normal capture on clock edge)
Cycle 4: rst_n=0, clk=0, d=1 → q=0 (asynchronous reset asserts between clock edges, immediately clearing q)

{
  "signal": [
    { "name": "clk",   "wave": "p......" },
    { "name": "rst_n", "wave": "01...01" },
    { "name": "d",     "wave": "1..0.1." },
    {},
    { "name": "q",     "wave": "0.10..1" }
  ],
  "head": { "text": "Asynchronous active-low reset behavior" }
}

• The output q must be registered and updated on the positive edge of clk.
• The reset condition must be evaluated asynchronously; q must become 0 immediately when rst_n goes low, without waiting for the next clock edge.
• The reset signal rst_n is active-low.
• The reset condition must take priority over any data capture.